1. Field of the Invention
The present invention relates to a method and an apparatus of manufacturing a semiconductor device. More particularly, the present invention relates to a method and an apparatus of manufacturing a semiconductor device, which have a process of polishing a wafer.
2. Description of Related Art
At a process of manufacturing a semiconductor device, there is a case of carrying out a polishing to flatten a surface. The polishing is carried out, for example, in a process of flattening an inter-layer insulating film, a process of forming an isolation of transistors, a process of forming a contact to connect a transistor and an upper wiring layer, a process of forming a metal wiring, and the like. There is a case that such surface polishing at those processes is carried out not only to flatten the surface but also to remove the unnecessary film.
For example, at the process of forming the contact and the process of forming the metal wiring, a concave portion is formed in an insulating film layer, and the metal film is embedded in this concave portion by using a sputtering method, a CVD method and the like. Here, the metal film is formed even on the surface except the concave portion. The metal film formed on a portion except the concave portion is required to be removed. Since the surface is polished, the metal film formed on the unnecessary portion is removed.
As one example of such polishing, the polishing at the process of forming the contact will be described below. FIGS. 1A, 1B are sectional views showing polishing targets before and after the polishing. FIG. 1A shows the sectional view before the polishing, and FIG. 1B shows the sectional view after the polishing. As shown in FIG. 1A, an inter-layer insulating film 3 is provided on a substrate 1. Holes 4 are formed in the inter-layer insulating film 3 to attain electric connections between an electrode and source/drain regions and an upper wiring layer. A metal film 2 including a lamination layer 21 made of TiN/Ti and a tungsten film layer 22 is embedded in the hole 4. When the metal film 2 is embedded by using the sputtering method or the CVD method, the metal film 2 is formed on the inter-layer insulating film 3 in addition to the holes 4, unless a special idea is applied. Since the metal film 2 formed on the portion except the holes 4 is unnecessary, this is removed by the polishing. By executing the polishing, the unnecessary metal film 2 is removed, as shown in FIG. 15.
In recent years, it is required that an excellent post-polishing shape is attained by such polishing process, because of the further superfine and complex device structure. On the other hand, it is an important object to improve productivity such as a throughput and the like, because of a request for mass productivity.
In conjunction with above explanations, Japanese Laid-Open Patent Application JP-P 2004-296596 A discloses a method of manufacturing a semiconductor device. An object is to attain a high throughput. The document discloses a polishing apparatus that has a plurality of polishing tables and polishing heads, wherein the number of polishing heads is greater than that of the polishing tables. The document discloses a process of attaching to and detaching from a semiconductor substrate with respect to the polishing head which is not used to polish.
Japanese Laid-Open Patent Application JP-P 2000-173959 A (corresponding to U.S. Pat. No. 6,432,825 B1, GB 2344459 A) discloses a method of manufacturing a semiconductor device. The document discloses a surface layer removing process of removing a metal film surface, wherein a polishing is carried out in at least two stages. In a first stage of the polishing, the polishing is executed under a high load. In a second stage of the polishing, the polishing is executed under a load lower than that of the first stage.
We have now discovered a following fact. When the polishing target is polished, there is a case that an over-polishing is carried out in order to remove the polishing residue resulting from the irregularity in the polishing. That is, after a surface layer of the polishing target is polished by a predetermined value, the over-polishing is further executed, thereby removing the polishing residue.
However, when the over-polishing is carried out, there is a case that the time (incubation time) appearing in the initial time of the polishing in which the polishing does not substantially progress becomes long. Such increase in the incubation time is severe when the surface on which both of the metal film and the insulating film are exposed is polished. As the incubation time becomes longer, the throughput becomes lower. Also, when the surface on which both of the metal film and the insulating film are exposed is over-polished, the metal material is apt to be eroded by a polishing solution in the incubation time. That is, the increases in a recess (recession of a wiring pattern caused by erosive action of chemical solution) and erosion (local recession of dense wiring) become problematic. As a reason of such problems, the fact may be considered that exposure of the insulating film causes a rise in a temperature to be difficult immediately after the over-polishing is started, and heat required to polish the metal film is not added.
JP-P 2000-173959 A discloses a technique that reduces the incubation time, when the entire surface of the wafer is the metal film. However, a technique for reducing the incubation time when the surface on which both of the metal film and the insulating film are over-polished is not described in any documents. Thus, the technique that can reduce the incubation time at the time of the over-polishing is desired.